Design and optimization techniques for VLSI Network on Chip architectures

Il sottosistema di interconnessione rappresenta una delle aree critiche nella progettazione di MPSoC, a causa di problemi relativi alla scalabilità a livello sia fisico che architetturale. Le architetture Network on Chip (NoCs) sono ritenute una promettente soluzione a tale problema. Tali architetture mirano alla soluzione di molte problematiche legate alla progettazione del l’interconnect portando a livello on-chip i paradigmi di comunicazione basati sulla commutazione a pacchetti. La lunghezza dei wire può essere controllata adattando la topologia alle caratteristiche fisiche e la banda di comunicazione disponibile può essere aumentata aggiungendo alla topologia nuovi switch e link. Argomenti principali della tesi sono la progettazione e la ottimizzazione delle architetture Network on Chip, entrambi affrontati rivolgendo particolare attenzione agli aspetti legati alle relazioni tra le decisioni prese a livello di sistema e le variabili collegate all’implementazione di back-end. In particolare il nucleo del lavoro di ricerca è un flusso completo per la progettazione di NoC application-specific. Il flusso proposto aiuta il progettista nello svolgimento di tutti i passi necessari alla progettazione, a partire dalla grafo di comunicazione relativo alla applicazione target sino alla fase di place&route. Il flusso proposto mira alla definizione della struttura NoC ottimale per una data applicazione. Il flusso consiste in una parte di front-end, deputata alla sintesi della configurazione di NoC ottimale, ottenuta sulla base delle richieste in termini di comunicazione poste dalla applicazione, in una parte di back-end, deputata alla implementazione a livello layout della configurazione scelta dal front-end, e in alcuni passi ausiliari necessari alla produzione delle informazioni che costituiscono la comunicazione e assicurano la coerenza tra le due parti

PMU-based distribution system state estimation with adaptive accuracy exploiting local decision metrics and IoT paradigm

A novel adaptive distribution system state estimation (DSSE) solution is presented and discussed, which relies on distributed decision points and exploits the Cloud-based Internet of Things (IoT) paradigm. Up to now, DSSE procedures have been using fixed settings regardless of the actual values of measurement accuracy, which is instead affected by the actual operating conditions of the network. The proposed DSSE is innovative with respect to previous literature, because it is adaptive in the use of updated accuracies for the measurement devices. The information used in the estimation process along with the rate of the execution are updated, depending on the indications of appropriate local metrics aimed at detecting possible variations in the operating conditions of the distribution network. Specifically, the variations and the trend of variation of the rms voltage values obtained by phasor measurement units (PMUs) are used to trigger changes in the DSSE. In case dynamics are detected, the measurement data are sent to the DSSE at higher rates and the estimation process runs consequently, updating the accuracy values to be considered in the estimation. The proposed system relies on a Cloud-based IoT platform, which has been designed to incorporate heterogeneous measurement devices, such as PMUs and smart meters. The results obtained on a 13-bus system demonstrate the validity of the proposed methodology that is efficient both in the estimation process and in the use of the communication resources

An FPGA platform for real-time simulation of spiking neuronal networks

In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments

Towards self-adaptive KPN applications on NoC-based MPSoCs

Self-adaptivity is the ability of a system to adapt itself dynamically to internal and external changes. Such a capability helps systems to meet the performance and quality goals, while judiciously using available resources. In this paper, we propose a framework to implement application level self-adaptation capabilities in KPN applications running on NoC-based MPSoCs. The monitor-controller-adapter mechanism is used at the application level. The monitor measures various parameters to check whether the system meets the assigned goals. The controller takes decisions to steer the system towards the goal, which are applied by the adapters. The proposed framework requires minimal modifications to the application code and offers ease of integration. It incorporates a generic adaptation controller based on fuzzy logic. We present the MJPEG encoder as a case study to demonstrate the effectiveness of the approach. Our results show that even if the parameters of the fuzzy controller are not tuned optimally, the adaptation convergence is achieved within reasonable time and error limits. Moreover, the incurred steady-state overhead due to the framework is 4% for average frame-rate, 3.5% for average bit-rate, and 0.5% for additional control data introduced in the network

ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge

CNN design and deployment on embedded edge-processing systems is an error-prone and effort-hungry process, that poses the need for accurate and effective automated assisting tools. In such tools, pre-evaluating the platform-aware CNN metrics such as latency, energy cost, and throughput is a key requirement for successfully reaching the implementation goals imposed by use-case constraints. Especially when more complex parallel and heterogeneous computing platforms are considered, currently utilized estimation methods are inaccurate or require a lot of characterization experiments and efforts. In this paper, we propose an alternative method, designed to be flexible, easy to use, and accurate at the same time. Considering a modular platform and execution model that adequately describes the details of the platform and the scheduling of different CNN operators on different platform processing elements, our method captures precisely operations and data transfers and their deployment on computing and communication resources, significantly improving the evaluation accuracy. We have tested our method on more than 2000 CNN layers, targeting an FPGA-based accelerator and a GPU platform as reference example architectures. Results have shown that our evaluation method increases the estimation precision by up to 5× for execution time, and by 2\times for energy, compared to other widely used analytical methods. Moreover, we assessed the impact of the improved platform-awareness on a set of neural architecture search experiments, targeting both hardware platforms, and enforcing 2 sets of latency constraints, performing 5 trials on each search space, for a total number of 20 experiments. The predictability is improved by 4\times , reaching, with respect to alternatives, selection results clearly more similar to those obtained with on-hardware measurements

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

This paper focuses on how to efficiently reduce power consumption in coarse-grained reconfigurable designs, to allow their effective adoption in heterogeneous architectures supporting and accelerating complex and highly variable multifunctional applications. We propose a design flow for this kind of architectures that, besides their automatic customization, is also capable of determining their optimal power management support. Power and clock gating implementation costs are estimated in advance, before their physical implementation, on the basis of the functional, technological, and architectural parameters of the baseline design. Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation

Palatovaginal (pharyngeal) artery: clinical implication and surgical experience

The palatovaginal or pharyngeal artery is a small branch of the internal maxillary artery supplying the nasopharynx. Bleeding from this artery is exceptional and only one case of traumatic epistaxis from this artery has been reported previously. We report a case of a 66-year-old male presenting with right recurrent posterior epistaxis. Endoscopic dissection of the pterygopalatine fossa and direct visualization of the palatosphenoidal canal permitted to identify the origin of bleeding, and coagulation of the pharyngeal artery solved the epistaxis. Although rare, intractable posterior epistaxis may arise from the pharyngeal artery. The anatomical knowledge of this artery and of the palatosphenoidal canal is of outmost importance in endoscopic transpterygoid and nasopharyngeal procedures, to identify the vidian canal, evaluate nasopharyngeal cancer spread in the pterygopalatine fossa, reduce bleeding during surgery of the nasopharynx, and harvest adequately the pedicle of the nasoseptal flap